RTL Engineer

 RTL Design Engineer

 Roles and responsibilities:

 • 3-5 years of industry experience

• Verilog HDL working knowledge is essential

• RTL Design and FPGA design flow working knowledge is must.

• Knowledge of an Operating System: UNIX / LINUX / Solaris

• Must have completed at least one front-end design cycle

• Should definitely have Simulation (Verilog-XL/NC/VCS/ModelSim/Questa) tool knowledge

• Sound Digital Design fundamentals • Domain knowledge in related areas of work such as PCIe, USB etc.

 Skill set: RTL Coding

FPGA Design Flow

Verilog HDL

Simulation tools

IP Protocols